About the Book

This book is a must primer for anyone who is beginning to learn synthesis using VHDL. A chapter on verification explains the many causes of simulation mismatches between pre and post synthesis models and on how to avoid these. Modeling guidelines are also provided to help improve synthesis results. - See the details of how VHDL gets translated into logic gates in this book. - Also, see how hardware elements are described in synthesizable VHDL!

Contents

1. Language Basics, 2. Synthesis Basics, 3. Mapping Statements to Gates, 4. Model Optimizations, 5. Verification, 6. Modeling Hardware Elements for Synthesis