Contents

1. VHDL Overview and Concepts. 2. Basic Language Elements. 3. Control Structures. 4. Drivers. 5. VHDL Timing. 6. Elements of Entity/Architecture. 7. Subprograms. 8. Packages. 9. User Defined Attributes, Specifications, and Configurations. 10. Design for Synthesis. 11. Functional Models and Testbenches. 12. UART Project. Appendix A: VHDL 93 and VHDL 87 Syntax Summary. Appendix B: Package Standard. Appendix C: Package Textio. Appendix D: STD_Logic_Textio. Appendix E: Package STD_Logic_1164. Appendix F: Numeric_STD. Appendix G: STD_Logic_Unsigned. AppendixH: STD_Logic_Signed. Appendix I: STD_Logic_Arith. Appendix J: STD_Logic_Misc. Appendix K: VHDL Predefined Attributes.