About the Book

The book provides a thorough understanding of the basics of the Verilog language, both from the features point of view and its usage in modeling. A number of examples for each language construct is provided; in addition, examples are provided to illustrate how collectively constructs can be used to model hardware. The various modeling styles supported by Verilog HDL are described in detail. The book explains how stimulus and control can also be described using the same Verilog language, including response monitoring and verification. The syntax of many of the constructs are shown in an easy to read manner, sometimes although not complete. This is done purposely to help explain the construct. The complete syntax of constructs of the Verilog language is provided in an appendix for reference

1. Basics, 2. Verilog Constructs to Gates, 3. Modeling Examples, 4. Model Optimizations, 5. Verification 

About the Author

J. Bhasker is the chair of the IEEE PAR 1364.1 verilog synthesis interoperability working Group that is working towards standardizing a Verilog subset for RTL synthesis. He is one of the main architects of the ArchSyn Synthesis system developed at Bell labs. He has taught Verilog HDL and Verilog HDL Synthesis to many AT & T / Lucent designers. He is also the author of the best selling book" A Verilog HDL Primer"